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IDT74LVC161A 3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER WITH ASYNCHRONOUS RESET, 5 VOLT TOLERANT I/O
* 0.5 MICRON CMOS Technology * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * All inputs, outputs, and I/Os are 5V tolerant * Supports hot insertion * Available in QSOP, SOIC, SSOP, and TSSOP packages
IDT74LVC161A
FEATURES:
DRIVE FEATURES:
* High Output Drivers: 24mA * Reduced system switching noise
APPLICATIONS:
* 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems
DESCRIPTION:
The LVC161A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS-compatible TTL families. The LVC161A is a presettable synchronous binary counter which
features an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaniously on the positive-going edge of the clock (CP). Outputs (Q0 to Q3) of the counters may be preset to a high or low level. A low level at the parallel enable input (PE) disables the counting action and causes the data at inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at the count enable inputs (CEP and CET). A low level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to low level regardless of the levels at CP, PE, CET, and CEP inputs (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be high to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a high output pulse of a duration approximately equal to a high level output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: 1 fmax = tp(max) (CP to TC) + tsu (CEP to CP) Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system.
FUNCTIONAL DIAGRAM
3 4 5 6
STATE DIAGRAM
0 1 2 3 4
D0
9
D1
D2
D3
PE
PARALLEL LOAD CIRCUITRY
15
5
10
CET TC
15
7
CEP
14
6
2
CP
BINARY COUNTER
13
7
1
MR
Q0
14
Q1
13
Q2
12
Q3
11
12
11
10
9
8
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c)1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-5156/1
IDT74LVC161A 3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
INDUSTRIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3
CET
CEP
PE
FF0 D CP CP Q RD Q D CP
FF1 Q D CP Q RD
FF2 Q D CP Q RD
FF3 Q
Q RD
MR
Q0
Q1
Q2
Q3
TC
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IDT74LVC161A 3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
INDUSTRIAL TEMPERATURE RANGE
TYPICAL TIMING SEQUENCE
MR PE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TSTG IOUT IIK IOK ICC ISS Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND Max -0.5 to +6.5 -65 to +150 -50 to +50 -50 100 Unit V C mA mA mA
D0 D1
D2
D3 CP
CEP
CET
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Q0
Q1
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT CI/O
INHIBIT
Q2
Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance
Conditions VIN = 0V VOUT = 0V VIN = 0V
Typ. 4.5 5.5 6.5
Max. 6 8 8
Unit pF pF pF
Q3
TC 12 RESET PRESET 13 14 15 0 COUNT 1 2
NOTE: 1. As applicable to the device type.
PIN CONFIGURATION
MR CP D0 D1 D2 D3 CEP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 CET PE
PIN DESCRIPTION
Pin Names MR CP Dx CEP GND PE CET Qx TC Vcc Description Asynchronous Master Reset (Active LOW) Clock Input (LOW-to-HIGH, Edge-Triggered) Data Inputs Count Enable Inputs Ground (0V) Parallel Enable Input (Active LOW) Count Enable Carry Input Flip-Flop Outputs Terminal Count Output Positive Supply Voltage
QSOP/ SOIC/ SSOP/ TSSOP TOP VIEW
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IDT74LVC161A 3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE (1)
OPERATING MODES Reset (clear) Parallel load Count Hold (do nothing)
NOTE: 1. H = h= L= l= X= *=
INPUTS MR L H H H H H CP X X X CEP X X X h l X CET X X X h X l PE X l l h h h Dx X l h X X X Qx L L H count Q(2) Q(2)
OUTPUTS TC L L * * * L
HIGH Voltage Level HIGH Voltage level one setup time prior to the LOW-to-HIGH clock transition. LOW Voltage Level LOW Voltage level one setup time prior to the LOW-to-HIGH clock transition. Don't care The TC output is HIGH when CET is HIGH and the counter is at Terminal Count (HHHH).
= LOW-to-HIGH clock transition 2. Indicates the state of the referenced output one set up time prior to the LOW-to-HIGH clock transition.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH(2) VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V, VIN = GND or VCC -- -- -- -- -- -0.7 100 -- 50 -1.2 -- 10 A V mV A VCC = 3.6V VO = 0 to 5.5V -- -- 10 A Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VI = 0 to 5.5V Test Conditions Min. 1.7 2 -- -- -- Typ.(1) -- -- -- -- -- Max. -- -- 0.7 0.8 5 A V Unit V
Quiescent Power Supply Current Variation
One input at VCC - 0.6V, other inputs at VCC or GND
--
--
500
A
NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. Clock Pin (CP) requires a minimum VIH of 2.5V.
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IDT74LVC161A 3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD Parameter Power Dissipation Capacitance Test Conditions CL = 0pF, f = 10Mhz Typical -- Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tW tW tREM tSU tSU tSU tH tSK(o) Parameter Propagation Delay CP to Qx Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay MR to Qx Propagation Delay MR to TC Clock Pulse Width, HIGH or LOW Master Reset Width LOW Removal Time, MR to CP Set-Up Time, Dx to CP Set-Up Time, PE to CP Set-Up Time, CEP, CET to CP Hold Time, Dx, PE, CEP, CET to CP Output Skew(2) 5 4 0.5 3.5 3.5 5.5 0 -- -- -- -- -- -- -- -- -- 4 3 0.5 3 3 5 0 -- -- -- -- -- -- -- -- 500 ns ns ns ns ns ns ns ps -- 11 -- 10 ns Min. -- -- -- -- Max. 9 11 8.8 10 VCC = 3.3V 0.3V Min. -- -- -- -- Max. 8 9.5 7.8 9 Unit ns ns ns ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2 Skew between any two outputs of the same package and switching in the same direction.
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IDT74LVC161A 3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 VCC(2)= 3.3V0.3V & 2.7V 6 2.7 1.5 300 300 50 Unit V V V mV mV pF
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
Propagation Delay
LVC QUAD Link
VCC 500 Pulse Generator
(1, 2)
VLOAD Open GND ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
LVC QUAD Link
VIN D.U.T. RT
VOUT
500 CL
LVC QUAD Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
DATA INPUT TIMING INPUT SYNCHRONOUS CONTROL ASYNCHRONOUS CONTROL
tSU
tH
tREM
INPUT
tPLH1
tPHL1
VIH VT 0V VOH VT VOL VOH VT VOL
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC QUAD Link
Set-up, Hold, and Release Times
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE VT
LVC QUAD Link
OUTPUT 1
tSK (x)
tSK (x)
VT
OUTPUT 2 tPLH2 tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC QUAD Link
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
Pulse Width
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IDT74LVC161A 3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
XX LVC XX XXXX IDT Device Type Package Temp. Range
Q DC PY PG 161A 74
Quarter Size Outline Package Small Outline IC Shrink Small Outline Package Thin Shrink Small Outline Package Presettable Synchronous 4-Bit Binary Counter with Asynchronous Reset, 5 Volt Tolerant I/O, 24mA -40C to +85C
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